`timescale 1ns/100ps
module tb;

parameter PERIOD = 500;
reg clk;
reg reset;
wire [15:0] AB;
reg [7:0] DI;
wire [7:0] DO;
wire WE;
reg IRQ;
reg NMI;
reg RDY;

reg [7:0] ROM [0:4095];

initial begin
    clk = 0;
    reset = 1;
    DI = 0;
    IRQ = 0;
    NMI = 0;
    RDY = 0;
    #10;
    reset = 0;
    #10;
    RDY = 1;
    $readmem("snake.rom1",ROM);
    #10;
end

always #(PERIOD/2) clk = ~clk;

cpu U_CPU( 
    .clk(clk),
    .reset(reset),
    .AB(AB),
    .DI(DI),
    .DO(DO),
    .WE(WE),
    .IRQ(IRQ),
    .NMI(NMI),
    .RDY (RDY ));

endmodule
